This invention relates to integrated circuit and, more particularly, to integrated circuits that are capable of performing floating-point arithmetic operations.
Floating-point operations are usually implemented in accordance with the IEEE754 standard, which defines a nonsubnormal floating-point number as consisting of a sign, a mantissa, and an exponent, where the mantissa is required to be normalized at all times because the standard implies a leading “1” (whereas subnormal numbers have all zero exponent bits with no implied one). Conventionally, normalization is performed using leading-zero counters and barrel shifters (i.e., circuits for left-shifting a number to be normalized by the number of zeros). However, performing normalization in this way is expensive in terms of circuit area and operational latency.
Integrated circuit such as programmable integrated circuits often include soft logic circuitry for implementing the leading-zero counters and the barrel shifters. In particular, the barrel shifters are typically implemented using a network of multiplexers. It may, however, be difficult to introduce additional pipeline stages into the network of multiplexers, which can limit the overall performance of the integrated circuit. It may therefore be desirable to shift the implementation of the normalization circuit into embedded hard logic resources that can be more easily pipelined.
It is within this context that the embodiments herein arise.